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Data Sheet
OXU121HP USB On-The-Go Full-Speed Host and High-Speed Peripheral Controller
Features
SinglechipUSBOTGfullspeedhostandhighspeedperipheral controller Replacestwochipsystem Reducessystemcostandboardspace Minimizessystemdesigncomplexityandpower consumption Simultaneoushostandperipheraloperation CompatiblewiththeUniversalSerialBusSpecification,Revision2.0 andtheOnTheGoSupplementtotheUSBSpecification2.0, Revision1.0 Single3.3Vpowersupply,flexibleI/Ovoltageof1.65Vto3.6V (LVCMOS/TTL)tointerfacetoawiderangeofMCUs Lowpoweroperation,suitableformobileapplications 30mA(max)forhostoperation 75mA(max)forperipheraloperation Powersavingmodeforthehostcontrollerandsuspendmodefor peripheralcontroller Integratedonchipchargepump,supportsupto100mAof current,enablessupportforbroadrangeofUSBdevices Smallpackageandfootprintsavesboardspace 7x7mmBGA,84ball,RoHScompliant 12x12mmLQFP,100pin,RoHScompliant 16bitmemorymappedinterfacecangluelesslyinterfacetomost popularmicroprocessorsandDSPs Fastmicroprocessoraccesscycleanddouble/multibuffering supportforallfourtypesofUSBtransfers TwoDMA(slave)channelsforthehighspeedperipheral controller,loweringCPUutilization IntegratedPLLsupportsexternalcrystalorcrystaloscillatorsof 12MHzand30MHz,forsystemflexibility 16KbytesofonchipSRAM,optimizedbuffersizefor performance/cost
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Allowsupto8bidirectionalendpointsandtransfersforsupport ofmultifunctionsystems ConfigurablehardwareHostNegotiationProtocol(HNP)and SessionRequestProtocol(SRP) Transactionschedulingandtransferlevelprotocolimplemented inhardware(includingdatatoggle,retryandbandwidth management)forhighperformance Operatingtemperaturerange:40to85degreesC
Device Overview
TheOxfordSemiconductorOXU121HP(formerlyTD1120)isasingle chipUSBOnTheGo(OTG)controllerthatincorporatesafullspeedhost andahighspeedperipheralcontroller.Itenablesanembeddedsystem tooperateasaUSBhostandaperipheralsimultaneously,thereby dramaticallyexpandingthedegreeofinterconnectivityandextending theapplicabilityofUSBintomanynewareas,especiallyinmobile communication,consumerelectronics,andprinterapplications.The combinationoftheOXU121HPhighspeedperipheralandfullspeed hostcontrollerenablesuserstoperformhighspeedUSBdatatransferfor peripheralconnectivitywhenconnectedtoahostdevice,andoperateat fullspeedinhostmodeoperationtomaximizesystembatterylifeina mobileenvironment. TheOXU121HPisidealformobileapplications.Itenableshighspeed PCsynchronizationtoreducedatafiletransfertimewhenoperatingin USBperipheralmode.Inhostmode,itenablesthesystemtoconnecttoa widerangeofUSBdevicessuchasflashdrives,keyboards,mice,and digitalstillcameras(DSC).Thesemobileapplicationsincludesmart phones,PDAs,MP3players,portablemediaplayers,digitalphoto albums,andGPSdevices. TheOXU121HPiswellsuitedforPictBridgeprinters.Itenableshigh speeddatatransferbetweenPCandprinter.Whileutilizingthehost port,itaddsPictBridgeprintingcapabilitytotheprintertosupport directphotoprintingfromaDSC.TheOXU121HPreplacesexistingtwo chipsolutionsbycombiningdiscretehostandperipheralcontrollersinto asinglechip,thusminimizingsystemcost,boardspace,design complexity,andpowerconsumption. TheOXU121HPallowsforsimultaneoushostandperipheraloperation. Theportscanbeconfiguredinoneoftwomodes: 1OTG+1Host:oneOTGportandonefullspeedhostport 1Peripheral+2Host:onehighspeedperipheralportandtwo fullspeedhostports SoftwaresolutionsfortheOXU121HPincludeUSBdevicedriversand theOxfordSemiconductorUSBLinkTMproductsuite.TheUSBLinkhost,
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OXU121HP Data Sheet
peripheral,andOTGstackshavebeenportedtoawidevarietyofreal timeoperatingsystemsincludingVxWorks(R),ThreadX(R),andNucleus(R). Inaddition,OxfordSemiconductoralsomakesavailablelowlevel controllerdriversforothernativeUSBstackssuchasthoseincludedwith Windows(R)CEandLinux(R)2.6.x. Figure1showstheOXU121HParchitecturaldiagram.
Figure 1 OXU121HP Architectural Diagram
OSC1 OSC2
Clock/ Osc Pads and Clk Div
ENVREG Voltage Regulator VBus Control Circuit and Vbus Charge Pump VREGOUT VBUS /EXVBO /PO /OC
ACK[1:0] REQ[1:0] DMA Interface System Configuration & Control Registers
HNP/SRP Logic /RESET /CS /WR /RD INT P Interface USB Peripheral Controller USB Peripheral Controller Registers
ID
P_DM P_DP
OTG XCVR A[12:1] D[15:0] USB Host Control Logic Host SIE & Root Hub Memory Blocks
DM1 DP1
TEST
Test Control
USB Host Controller Registers
USB Xcvr
DM2 DP2
Development Support
TheOXU121HPproductsuiteincludestheUSBcontrolleraswellasthe protocolstacksandthedriversoftwarethatenableawidevarietyofUSB applications.Thisuniqueabilitytodeliveratotalhardwareandsoftware solutionsetsOxfordSemiconductorapartfromothersemiconductor companiesandbenefitscustomersby: Shorteningtimetomarket Reducingrisk Offeringasinglesourceforhardwareandsoftware,thereby reducingthenumberofsuppliersthecustomerhastodealwith OxfordSemiconductorisaMicrosoft(R)Windows(R)EmbeddedPartner andhasdevelopedhostandperipheralcontrollerdriversforWindows CE5.0.SimilarsoftwaresupportisalsoavailableforLinux(R)2.6.x.
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Forcustomersusingarealtimeoperatingsystem(RTOS)suchas VxWorks(R),ThreadX(R),Nucleus(R),OSE,LynxOS(R)andAMXTMamong others,OxfordSemiconductoroffersitsUSBLinkhost,peripheraland OnTheGosoftwaresolutions. TheUSBLinkProductSuiteisamodularizedapproachtoprovidingUSB connectivityforawidevarietyofembeddedproducts.Duetoitsflexible architectureandbroadbasedsupportforUSBhost,peripheralandOTG applications,OxfordSemiconductorcantailortheUSBLinksoftware deliverablestomeeteachcustomer'sUSBrequirements. TheUSBLinksolutionsareconfigurableandcansupportsystemswith: Bigorlittleendianprocessors DMAornonDMAUSBcontrollers AwidevarietyofUSBcontrollers,includingtheOXU121HP Abroadrangeofoperatingsystems OxfordSemiconductorhasovereightyearsofexperiencedeveloping embeddedUSBtechnology.ItsUSBLinksoftwarehasbeenportedto twentydifferentoperatingsystemsandawidevarietyofembedded architectures.USBLinkisshippinginmanymillionsofunits.
Sample Applications
Portablemediaplayers MP3players Caraudio&navigation Printers Smartmobilephones Digitaltelevisions Homemediacenters Digitalvideocameras Digitalstillcameras Externalstorageproducts SetTopBoxes(STB) PersonalVideoRecorders(PVR) PersonalDigitalAssistants(PDA) DVDrecorders
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OXU121HP Data Sheet
Electrical Characteristics
Symbol VDD3.3 VDD1.8 VDDW VI TS
Note:
Tables3to11detailtherequiredoperatingconditionsforthedeviceand theDCandACelectricalcharacteristics.
Table 1 Absolute Maximum Device Ratings Parameter 3.3 V power supply 1.8 V power supply 1.8 V to 3.3 V power supply DC input voltage Storage temperature
1
Condition
Min -0.3 -0.3 -0.3 -0.3 -40
Max 4.0 2.16 4.0 4.0 +150
Unit V V V V C
Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded. Functionaloperationshouldberestrictedtothenormaloperatingconditionsspeci fiedinthefollowingsection.Exposuretoabsolutemaximumratingconditionsfor extendedperiodsmayaffectdevicereliability.
Table 2 Recommended Operating Conditions Symbol VDD3.3 VDD1.8 VDDW VI3.3 VIW TO Parameter 3.3 V power supply 1.8 V power supply 1.8 - 3.3 V wide-range I/O power supply DC input voltage of 3.3 V pins DC input voltage of wide-range pins Operating temperature Condition Min 2.97 1.62 1.62 0 0 -40 Max 3.63 1.98 3.63 3.6 1.1*VDDW +85 Unit V V V V V C
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Table 3 DC Characteristics, Full-Speed USB I/O Signals: DP1, DP2, DM1, DM2 Symbol VDI VCM VOL VOH VCRS CIN Parameter Diff. input sensitivity Diff. comm. mode range Static output low Static output high Output signal crossover Input capacitance Condition |VI(DPN) -- VI(DMN)| (where N = 1 or 2) Min 0.2 0.8 0.0 2.8 1.3 2.5 0.3 3.6 2.0 20 Max Unit V V V V V pF
Table 4 DC Characteristics, High-Speed USB I/O Signals: DPP and DMP Only Symbol VHSDIFF VHSCM VHSSQ VHSIO VHSOL VHSOH VCHIRPK Parameter High-speed differential input sensitivity High-speed data signaling common mode range High-speed squelch detection threshold High-speed idle output voltage (differential) High-speed low-level output voltage (differential) High-speed high-level output voltage (differential) Chirp-K output voltage (differential) Squelch detected No squelch detected 150 -10 -10 -360 -900 10 10 400 -500 Condition |VI(DPP) -- VI(DMP)| Min 300 -50 500 100 Max Unit mV mV mV mV mV mV mV mV
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OXU121HP Data Sheet
Table 5 DC Characteristics, Logic Signals Symbol VOL VOH VIL VIH CIN COUT CBI IIN
Note:
Parameter Low-level output voltage High-level output voltage Low-level input voltage High-level input voltage Input capacitance Output capacitance Bi-directional capacitance Input leakage current VDDW = 3.3 V VDDW = 1.8 V VDDW = 3.3 V VDDW = 1.8 V VDDW = 3.3 V VDDW = 1.8 V
Condition
Min 2.4
0.75*VDDW
Max 0.4
Unit V V V
0.8 0.3*VDDW 2.0 0.7*VDDW 2.2 (typical) 2.2 (typical) 2.2 (typical)
V V V V pF pF pF A
No pull up or pull down
-10
10
Thecapacitanceslistedabovedonotincludepadcapacitanceandpackagecapacitance. Onecanestimatepincapacitancebyaddingpadcapacitanceofabout0.5pF;andthe packagecapacitance,whichisabout0.86pFmaxforQFPand0.42pFmaxforBGA.
Table 6 DC Characteristics, ID Resistance Symbol RB-PLUG-ID RA-PLUG-ID Parameter Resistance to ground on mini-B plug Resistance to ground on mini-A plug Condition Min 100 K 10 Max Unit
Table 7 DC Characteristics, Regulator Symbol RVout RIdrive Rtst
Note:
Parameter Output voltage Driving current Start-up time when enabled
Condition Driving current <= 100 mA VDD3.3A = 3.3 V Output voltage = 1.8 V VDD3.3A = 3.3 V RVout = 1.62 V (90%)
Min
Max 150
Unit V mA s
1.8 (typical)
25 (typical)
TheVDD3.3ApinthatcorrespondstotheregulatorsupplyisQFPpin81andBGApinB9.
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Table 8 DC Characteristics, Charge Pump Symbol CVout VDD1.8 VDDW
Note:
Parameter Output voltage Driving current Start-up time when enabled
Condition Driving current <= 100 mA VCPSUPPLY = 3.3 V Output voltage = 5 V VCPSUPPLY = 3.3 V RVout = 4.5 V (90%)
Min 4.75
Max 5.07 100
Unit V mA s
400 (typical)
ThechargepumpsupplyVCPSUPPLYsuppliestheexternalcomponentsofthecharge pumpcircuit.
Table 9 AC Characteristics, High-Speed DPP and DMP Driver Characteristics Symbol tHSR tHSF RDRV Parameter High-speed differential rise time High-speed differential fall time Driver output impedance Equivalent resistance used as internal chip Condition Min 500 500 40.5 49.5 Max Unit ps ps
Table 10 AC Characteristics, Full-Speed DP1, DP2, DM1, DM2 Driver Characteristics Symbol tFR tFF tFRFM ZDRV Rise time Fall time TR/TF matching Driver output resistance Steady state drive with external 33 series resistor Parameter CL = 50 pF CL = 50 pF Condition Min 4 4 90 3 Max 20 20 110 9 Unit ns ns %
Table 11 AC Characteristics, Low-Speed DP1, DP2, DM1, DM2 Driver Characteristics Symbol tLR tLF tFRFM Rise time Fall time TR/TF matching Parameter Condition CL = 200 - 600 pF CL = 200 - 600 pF Min 75 75 80 Max 300 300 125 Unit ns ns %
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OXU121HP Data Sheet
Power Consumption
Table12givestypicalpowerconsumptionfiguresfortheOXU121HP.
Table 12 OXU121HP Power Consumption Condition Host operational current Peripheral operational current ENVREG = 1 High-speed, ENVREG = 1 Full-speed, ENVREG = 1 Host suspend state current Peripheral suspend state current Power save state current ENVREG = 1 ENVREG = 1 ENVREG = 1 Min Max 30 75 50 150 (typical) 400 (typical) 150 (typical) Unit mA mA mA A A A
Theabovemeasurementsareattypicalprocesscornerandroom temperatureanddonotaccountforprocessandtemperaturevariations. Peripheraloperationalcurrentismeasuredwith5mcablewith maximumswitchingandBULKOUTtransferat400Mbpswith92.6% busutilizationduringonemicroframe.Theactualaveragecurrentin customerapplicationswillbelower.
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Pin Layout
TheOXU121HPissuppliedasa100pinLQFPpackageandasa84ball BGApackage.Figure2showsthechiplayoutofthe100pinLQFP package.
Figure 2 OXU121HP 100-Pin LQFP Package (Top View)
PD_PMOS CLKCFG XMODE /EXVBO
VDD 3.3A
VDD 3.3A
VOUT
VBUS
VDD 1.8
VDD 1.8
VDD 3.3
EXT
V DD1.8
VSSA
VSSA
VBP
DM1
/OC
/PO
DP1
75 DP2 DM2 VDD3.3 ENVREG VREGOUT VDD3.3A VSSA VSS V DD1.8 VDDW /RESET TEST GPIO DRQ 0 ACK 0 RSVD 0 DRQ 1 ACK 1 RSVD 1 VDDW D0 D1 D2 D3 V DD1.8 . 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1
VSS
74
73
72 71
70
69
68
67 66
65 64
63
62
61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 OSC 1 OSC 2 VDD3.3A VSSA RREF DMP DPP VDD3.3A VSSA VSS V DD1.8 . /CS NC ATEST13 A12 A11 A10 A9 A8 V DDW A7 A6 A5 VSS VDDW
VSS
VSS
VSS
NC A3
ID
OXU121HP-LQBG
37 36 35 34 33 32 31 30 29 28 27 26
2
D4
3
D5
4
D6
5
D7
6
V DD1.8
7
V DDW
8
D8
9
D9
10
D 10
11 12
D 11 VSS
13 14
D 12 D 13
15
D 14
16
D 15
17
V DDW
18
V DD1.8
19
INT
20
/WR
21 22
A1 /RD
23 24 25
A2 A4
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OXU121HP Data Sheet
Table13liststheLQFPpinallocations.
Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 1 of 3) Pin No. Bits 16 Type(1) Name Description
Processor Interface (37 pins) 2, 3, 4, 5, 8, 9, 10, 11, 13, 14, 15, 16, 96, 97, 98, 99 22, 23, 24, 25, 28, 29, 30 32, 33, 34, 35, 36 20 21 39 19 MSBCT D0 - D15 16-bit data bus. Pull-up/pull-down can be controlled through register 0x034, bits 2:1. Default is none Address bus for direct address space of 8 Kbytes. Pull-up can be enabled through register 0x034, bits 9:8. Default is pull-down Write strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up Read strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up Chip select. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up Interrupt to the MCU.This pin can be software configured as a driven output or open drain. Open drain is the default Hardware reset. Pull-up is always enabled DMA request outputs to support two channels DMA acknowledge. Pull-up/pull-down can be controlled through register 0x03A, bits 1:0. Default is none General purpose I/O Digital/wide-range ground Analog ground 1.8 V core power. VREGOUT may be used for the supplies Analog +3.3 V power Digital +3.3 V power Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V, VREGOUT may be used for these supplies Data lines for host port 2, a dedicated USB host port. If not used, these pins should be left floating Data lines for host port 1, which can serve as a USB host or an OTG port in combination with the peripheral port. If not used, these pins should be left floating
12
MSID
A1 - A12
1 1 1 1
MSIU MSIU MSIU MOCT
/WR /RD /CS /INT
86 89, 92 90, 93
1 2 2
MSIU MOCT MSI
/RESET DRQ1, DRQ0 ACK1, ACK0
General Purpose I/O (1 pin) 88 1, 12, 27, 41, 51, 65, 75, 83 42, 47, 69, 74, 82 6, 18, 40, 53, 57, 66, 84, 100 43, 48, 70, 73, 81 56, 78 7, 17, 26, 31, 85, 95 76, 77 54, 55 1 8 5 8 5 2 6 BC GPIO VSS VSSA VDD1.8 VDD3.3A VDD3.3 VDDW Power & Ground (34 pins)
USB Interface (13 pins) 2 2 B B DP2, DM2 DP1, DM1
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 2 of 3) Pin 44, 45 No. Bits 2 Type(1) B DPP, DMP Name Description Data lines for USB peripheral port, which can serve as an OTG port in combination with host port 1. If not used, these pins should be left floating Connect external reference resistor (12 K +/- 1%) to VSSA VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host-only application VBUS pulsing control. This pin is used only when the OTG port is operating as a B-device Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0: VBUS on) when using the external VBUS source Over current condition indicator for powered host ports. Pull-up is always enabled Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip's responsibility in an OTG application (0: A-device, 1:B-device). Pull-up can be disabled through register 0x038, bits 7:6. Default is pull-up Turn on/off gang power for all host ports Input. A 12 MHz or 30 MHz passive crystal should be connected across the two pins (OSC1 and OSC2). Optionally, a 12 MHz or 30 MHz oscillator can be connected to OSC1 while keeping OSC2 unconnected Output Indicates whether a 12 MHz or a 30 MHz crystal/ oscillator is being used. 0 = 12 MHz crystal or 12 MHz 3.3 V oscillator input on OSC1 1 = 30 MHz crystal or 30 MHz 3.3 V oscillator input on OSC1 Internal charge pump output for P-MOSFET (optional switch on the VOUT) Internal charge pump output for N-MOSFET Internal charge pump output voltage feedback pin Enables the internal voltage regulator if asserted. If not used, this pin should be tied to VSS
46 72
1 1
B 5I
RREF VBUS
60 59
1 1
OC O
VBP /EXVBO
58 62
1 1
IU IU
/OC ID
61 50
1 1
O I
/PO OSC1
Clock Interface (3 pins)
49 63
1 1
O I
OSC2 CLKCFG
Internal VBUS Charge Pump (3 pins) 68 71 67 79 1 1 1 1 O O I I PD_PMOS EXT VOUT ENVREG
Internal Voltage Regulator (2 pins)
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OXU121HP Data Sheet
Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 3 of 3) Pin 80 No. Bits 1 Type(1) O Name VREGOUT Description Internal voltage regulator output of 1.8 V. If enabled, this output should be connected to the VDD1.8 (and VDDW if wide-range IO is at 1.8 V) supplies of the chip. If the regulator is disabled, then this pin should be treated as another VDD1.8 supply input to the chip Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation. Pull-down is always enabled Additional address pin for debug use. Should be grounded or left floating (has an internal pull down) for normal use. Pull-down is always enabled This pin must be grounded for normal operation Reserved No connection. This pin should be left floating
Test (3 pins) 87 1 ID TEST
37
1
ID
ATEST13
64 91, 94 38, 52
NotetoTable13:
1 2 2
I 1
XMODE RSVD0, RSVD1 NC
Miscellaneous (4 pins)
Typekey:formatis[(L)(W_)X(Y)(_Z(A))]wherethefollowingconventionsapply:
L--Logic Level M(2) Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS Schmitt Trigger
W--Tolerance 5 5V 3.3 V I O B
2 3
X--Type Input Output Bidirectional U D
Y--Pull Pull up Pull down None
Z--Drive C(3)
T--Tristate T Tristate Normal
S
Programto3.3,2.5,or1.8VbysettingtheVIOvoltagelevel. Programto2mA,4mA,6mA,8mA,10mA,12mA,14,mA,or16mAviatheI/OConfigura tionRegister(0x034).
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Figure3showsthechiplayoutofthe84ballBGApackage.
Figure 3 OXU121HP 84-Ball BGA Package (Top View)
10 9 8
7 6 5 4 3 2 1
DM2
VSSA
V SSA
EXT
VOUT
XMODE
/PO
/OC
DP1
OSC 1
DP2
VDD3.3A
VDD3.3A
VDD3.3A
PD_PMOS
CLKCFG
VBP
DM 1
OSC 2
V DD3.3A
VREGOUT
ENVREG
VSS
VBUS
VSSA
ID
/EXVBO
V DD3.3
R REF
V SSA
TEST
GPIO
DRQ 0
V DD3.3A
DPP
DM P
DRQ 1
/RESET
VDD3.3
VSS
/CS
V SSA
ACK0
RSVD0
V DD1.8
OXU121HP-PBBG
V DDW
A 12
ATEST13
ACK 1
RSVD1
D1
A10
A9
A 11
D0
D2
VSS
D11
VDD1.8
VDDW
/WR
VDD1.8
A7
A8
D3
D6
D8
D10
D 13
D14
INT
A2
A3
A5
D4
D5
D7
D9
D 12
D15
/RD
A1
A4
A6
A
B
C
D
E
F
G
H
J
K
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OXU121HP Data Sheet
Table14liststheBGApinallocations.
Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 1 of 3) Pin No. Bits 16 Type(1) Name Description
Processor Interface (37 pins) A3, C4, B3, A2, A1, B1, B2, C1, C2, D1, D2, D3, E1, E2, F2, F1 H1, H2, J2, J1, K2, K1, J3, K3, J4, H4, K4, J5 G3 G1 J6 G2 MSBCT D0 - D15 16-bit data bus. Pull-up/pull-down can be controlled through register 0x034, bits 2:1. Default is none
12
MSID
A1 - A12
Address bus for direct address space of 8 Kbytes. Pull-up can be enabled through register 0x034, bits 9:8. Default is pull-down Write strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up Read strobe. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up Chip select. Pull-up can be disabled through register 0x034, bit 13. Default is pull-up Interrupt to the MCU.This pin can be software configured as a driven output or open drain. Open drain is the default Hardware reset. Pull-up is always enabled DMA request outputs to support two channels DMA acknowledge. Pull-up/pull-down can be controlled through register 0x03A, bits 1:0. Default is none General purpose I/O Digital ground Analog ground 1.8 V core power. VREGOUT may be used for these supplies Analog +3.3 V power Digital +3.3 V power Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V, VREGOUT may be used for these supplies Data lines for host port 2, a dedicated USB host port. If not used, these pins should be left floating Data lines for host port 1, which can serve as a USB host or an OTG port in combination with the peripheral port. If not used, these pins should be left floating Data lines for USB peripheral port, which can serve as an OTG port in combination with host port 1. If not used, these pins should be left floating
1 1 1 1
MSIU MSIU MSIU MOCT
/WR /RD /CS /INT
B6 C7, A6 A5, A4
1 2 2
MSIU MOCT MSI
/RESET DRQ0, DRQ1 ACK1, ACK0
General Purpose I/O (1 pin) B7 C3, C8, H6 B10, C10, E8,K6, K8 C5, E3, H3 B9, C9, D9, H7, K9 C6, H8 F3, H5 USB Interface (13 pins) A9, A10 J10, H9 2 2 B B DP2, DM2 DP1, DM1 1 3 5 3 5 2 2 B GPIO VSS VSSA VDD1.8 VDD3.3A VDD3.3 VDDW Power & Ground (20 pins)
J7, K7
2
B
DPP, DMP
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 2 of 3) Pin D8 No. Bits 1 5I Type(1) VBUS Name Description VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host only application VBUS pulsing control. This pin is used only when the OTG port is operating as a B-device Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0:VBUS on) when using the external charge pump Over current condition indicator for powered host ports. Pull-up is always enabled Connect external reference resistor (12 K +/- 1%) to VSSA Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip's responsibility in an OTG application (0: A-device, 1:B-device). Pull-up can be disabled through register 0x038, bits 7:6. Default is pullup Turn on/off gang power for all host ports Input. A 12 MHz or 30 MHz passive crystal should be connected across the two pins (OSC1 and OSC2). Optionally, a 12 MHz or 30 MHz oscillator can be connected to OSC1 while keeping OSC2 unconnected Output Indicates whether a 12 MHz or a 30 MHz crystal/oscillator is being used. 0 = 12 MHz crystal or 12 MHz 3.3 V oscillator input on OSC1 1 = 30 MHz crystal or 30 MHz 3.3 V oscillator input on OSC1 Internal charge pump output for P-MOSFET (optional switch on the VOUT) Internal charge pump output for N-MOSFET Internal charge pump output voltage feedback pin Enables the internal voltage regulator if asserted. If not used, this pin should be tied to VSS Internal voltage regulator output of 1.8 V. If enabled, this output should be connected to the VDD1.8, (and VDDW if wide-range IO is at 1.8 V) supplies of the chip. If the regulator is disabled, then this pin should be treated as another VDD1.8 supply input to the chip
G9 G8
1 1
OC P5O
VBP /EXVBO
H10 J8 F8
1 1 1
IU B IU
/OC RREF ID
G10 Clock Interface (3 pins) K10
1 1
P5O I
/PO OSC1
J9 F9
1 1
O I
OSC2 CLKCFG
Internal VBUS Charge Pump (3 pins) E9 D10 E10 B8 A8 1 1 1 1 1 O O I I O PD_PMOS EXT VOUT ENVREG VREGOUT
Internal Voltage Regulator (2 pins)
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Oxford Semiconductor, Inc.
OXU121HP Data Sheet
Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 3 of 3) Pin Test (3 pins) A7 1 ID TEST Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation. Pull-down is always enabled Additional address pin for debug use. Should be grounded or left floating (has an internal pull down) for normal use. Pull-down is always enabled This pin must be grounded for normal operation Reserved No. Bits Type(1) Name Description
K5
1
ID
ATEST13
F10 Miscellaneous (2 pins) B5, B4
NotetoTable14:
1 2
1
I -
XMODE RSVD0, RSVD1
Typekey:formatis[(L)(W_)X(Y)(_Z(A))]wherethefollowingconventionsapply:
L--Logic Level M
(2)
W--Tolerance 5 5V 3.3 V I O B
2 3
X--Type Input Output Bidirectional U D
Y--Pull Pull up Pull down None
Z--Drive C
(3)
T--Tristate T Tristate Normal
Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS Schmitt Trigger
S
Programto3.3,2.5,or1.8VbysettingtheVIOvoltagelevel. Programto2mA,4mA,6mA,8mA,10mA,12mA,14,mA,or16mAviatheI/OConfigura tionRegister(0x034).
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Package Layout
Figure 4 100-Pin LQFP
Figure4showsthepackagelayoutforthe100pinLQFPpackage.
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Oxford Semiconductor, Inc.
OXU121HP Data Sheet
Figure5showsthelayoutforthe84ballTFBGA.
Figure 5 84-Ball TFBGA Package
1 of 2
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
Figure 5 84-Ball TFBGA Package (continued)
2 of 2
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Oxford Semiconductor, Inc.
OXU121HP Data Sheet
Ordering Information
ThefollowingconventionsareusedtoidentifyOxfordSemiconductor products.
OXU121HP - LQBG Green (RoHS compliant) Revision Package Type: LQ Part Number 100-Pin LQFP
OXU121HP - PBBG Green (RoHS compliant) Revision Package Type: PB Part Number 84-Ball TF-BGA
Contacting Oxford Semiconductor Revision Information
SeetheOxfordSemiconductorwebsite(http://www.oxsemi.com)for furtherdetailaboutOxfordSemiconductordevices,oremail sales@oxsemi.com.
Table15documentstherevisionsofthisguide.
Table 15 Revision Information Revision August 06 First publication Modification
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OXU121HP Data Sheet
Oxford Semiconductor, Inc.
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(c) Oxford Semiconductor, Inc. 2006 The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in this document.
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